Product Documentation

FairCom ISAM for C

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Multi-CPU Performance

A cache-line is the smallest amount of memory a processor will retrieve and store in its highest speed cache. Typical cache-line sizes are 16, 32 or 64 bytes. On multiple CPU systems, when a memory word is updated, any other processor with a cache-line containing the updated word must eliminate or refresh the cache-line. When the other processors are not actually using the particular word that was updated, this is called false-sharing.

Many of the Server’s high use objects (e.g., semaphores, mutexes, transaction related arrays) are structured and/or allocated in a manner sensitive to the false sharing problem. This minimizes performance loss from false-sharing. Semaphores and mutexes are allocated to ensure each semaphore exists in its own cache-line and an update in one semaphore’s state by a CPU will not cause other CPUs to synchronize cache.

The cache-line size defaults to 16 and may be overridden with a configuration entry of the form: CACHE_LINE <size>. Set this value to the appropriate value for your CPU, as described above, to maximize performance.